Nonvolatile memory device including a fast read page and a storage device including the same

ABSTRACT

A nonvolatile memory device including: a memory cell array, the memory cell array including a plurality of cell strings, at least one of the cell strings including a plurality of memory cells stacked in a direction perpendicular to a surface of a substrate, at least one of the memory cells is a multi-level cell storing at least three bits; and a control logic circuit configured to control a page buffer to read a fast read page of the memory cells with one read voltage and at least two normal read pages of the memory cells with the same number of read voltages.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority under 35 U.S.C. § 119 to Korean PatentApplication No. 10-2019-0102178 filed on Aug. 21, 2019, in the KoreanIntellectual Property Office, the disclosure of which is incorporated byreference herein in its entirety.

TECHNICAL FIELD

The inventive concept relates to a nonvolatile memory device.

DISCUSSION OF RELATED ART

Semiconductor memories may be classified as volatile memory devices ornonvolatile memory devices. Volatile memory devices lose data storedtherein in the absence of power. Examples of volatile memory devicesinclude a static random access memory (SRAM), a dynamic RAM (DRAM), anda synchronous DRAM (SDRAM). Nonvolatile memory devices retain datastored therein even in the absence of power. Examples on nonvolatilememory devices include a read only memory (ROM), a programmable ROM(PROM), an electrically programmable ROM (EPROM), an electricallyerasable and programmable ROM (EEPROM), a flash memory device, aphase-change RAM (PRAM), a magnetic RAM (MRAM), a resistive RAM (RRAM),and a ferroelectric RAM (FRAM).

Various program techniques are used to increase the number of data bitsto be stored per memory cell. However, certain data is required to beprogrammed in a single level cell (SLC) program scheme to maintain itsreliability. However, when performing SLC programming on an entirememory block, even though data reliability is secured, there is a lossof storage space.

SUMMARY

An exemplary embodiment of the inventive concept provides a nonvolatilememory device comprising: a memory cell array, the memory cell arrayincluding a plurality of cell strings, at least one of the cell stringsincluding a plurality of memory cells stacked in a directionperpendicular to a surface of a substrate, at least one of the memorycells is a multi-level cell storing at least three bits; and a controllogic circuit configured to control a page buffer to read a fast readpage of the memory cells with one read voltage and at least two normalread pages of the memory cells with the same number of read voltages.

An exemplary embodiment of the inventive concept provides an operatingmethod of a storage device including a memory controller and anonvolatile memory device, the method comprising: receiving a commandfor reading data from a fast read page of the nonvolatile memory device;and providing the data read from the fast read page to the memorycontroller through a data line, wherein the fast read page is read withone read voltage, wherein the nonvolatile memory device includes aplurality of cell strings, at least one of the cell strings including aplurality of memory cells stacked in a direction perpendicular to asurface of a substrate, at least one of the memory cells is amulti-level cell storing at least three bits.

An exemplary embodiment of the inventive concept provides a storagesystem comprising: a storage device that exchanges a signal with anexternal device, wherein the storage device includes a memory controllerand a plurality of nonvolatile memories, wherein at least one of thememories includes: a memory cell array, the memory cell array includinga plurality of memory cells stacked in a direction perpendicular to asurface of a substrate; and a control logic circuit configured tocontrol a page buffer to read a fast read page of the memory cells withone read voltage and at least two normal read pages of the memory cellswith the same number of read voltages.

An exemplary embodiment of the inventive concept provides a memorydevice comprising: a memory controller, and a nonvolatile memory deviceconnected to the memory controller, wherein the memory controller isconfigured to perform a read operation on the nonvolatile memory devicesuch that a fast read page of the nonvolatile memory device is read withone read voltage and at least two normal read pages of the nonvolatilememory device are read with the same number of read voltages.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other features of the inventive concept will become moreapparent by describing in detail exemplary embodiments thereof withreference to the accompanying drawings.

FIG. 1 illustrates a storage device according to an exemplary embodimentof the present inventive concept.

FIG. 2 illustrates a memory controller illustrated in FIG. 1.

FIG. 3 illustrates a nonvolatile memory device of FIG. 1.

FIG. 4 is a circuit diagram illustrating a memory block BLK of aplurality of memory blocks included in a memory cell array of FIG. 3.

FIG. 5 illustrates an operating method of a storage device according toan exemplary embodiment of the present inventive concept.

FIG. 6 is a timing diagram for describing an operating method of astorage device of FIG. 5.

FIG. 7 illustrates a bit ordering and threshold voltage distributions ofmemory cells programmed based on the bit ordering, according to anexemplary embodiment of the present inventive concept.

FIG. 8 is a timing diagram for describing an operating method of astorage device according to an exemplary embodiment of the presentinventive concept.

FIG. 9 illustrates a fast read page read and a normal read page read ofa storage device when a read operation is performed according to anexemplary embodiment of FIG. 8.

FIG. 10 illustrates a page read of a storage device when a readoperation of the storage device is performed according to a normal bitordering.

FIG. 11 illustrates a bit ordering according to an exemplary embodimentof the present inventive concept.

FIG. 12 illustrates a bit ordering according to an exemplary embodimentof the present inventive concept.

FIG. 13 illustrates a bit ordering according to an exemplary embodimentof the present inventive concept.

FIG. 14 illustrates a portion of a circuit diagram of FIG. 4.

FIG. 15 illustrates an operating method of a storage device according toan exemplary embodiment of the present inventive concept.

FIG. 16 is a timing diagram for describing an operating method of astorage device of FIG. 15.

FIG. 17 is a timing diagram for describing an operating method of astorage device of FIG. 15.

FIG. 18 is a table illustrating the average number of read voltagesrequired to determine page data depending on a page type.

FIG. 19A is a table illustrating a read time taken to determine pagedata depending on a page type.

FIG. 19B is a graph illustrating read times for respective page types ofFIG. 19A.

FIG. 20 is a graph illustrating the number of error bits associated withthe number of bits to be stored per memory cell, for each page type.

FIG. 21 illustrates a storage system to which a memory controller and anonvolatile memory device according to an exemplary embodiment of theinventive concept are applied.

FIG. 22 illustrates a memory card to which a nonvolatile memory deviceaccording to an exemplary embodiment of the inventive concept isapplied.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Below, exemplary embodiments of the inventive concept will be describedin detail with reference to the accompanying drawings. Like referencenumerals may refer to like elements in the drawings.

Hereinafter, components that are described with reference to the terms“unit”, “module”, “block”, etc. and function blocks illustrated indrawings may be implemented with software, hardware, or a combinationthereof. For example, the software may be machine code, firmware,embedded code, or application software. For example, the hardware mayinclude an electrical circuit, an electronic circuit, a processor, acomputer, an integrated circuit, integrated circuit cores, a pressuresensor, an inertial sensor, a microelectromechanical system (MEMS), apassive element, or a combination thereof.

FIG. 1 illustrates a storage device 100 according to an exemplaryembodiment of the present inventive concept.

The storage device 100 includes a memory controller 110 and anonvolatile memory device 120. For example, the nonvolatile memorydevice 120 may include a plurality of nonvolatile memories. Thenonvolatile memories may be connected to the memory controller 110through a plurality of channels. In this case, at least two or morenonvolatile memories may be connected to each channel.

The memory controller 110 may control a read operation and a writeoperation of the nonvolatile memory device 120. For example, the memorycontroller 110 may transfer a command CMD, an address ADDR, and data“DATA” to the nonvolatile memory device 120 by using a plurality of datasignals DQ. Alternatively, by using the plurality of data signals DQ,the memory controller 110 transfers the command CMD and the address ADDRto the nonvolatile memory device 120 and receives the data “DATA” fromthe nonvolatile memory device 120. The memory controller 110 transferscontrol signals CTRL and a data strobe signal DQS to the nonvolatilememory device 120.

In an exemplary embodiment of the inventive concept, the control signalsCTRL, the data strobe signal DQS, and the plurality of data signals DQmay be transferred to the nonvolatile memory device 120 throughdifferent signal lines, independently of each other. The control signalsCTRL and the data strobe signal DQS may be used to identify theplurality of data signals DQ that are transferred from the memorycontroller 110 to the nonvolatile memory device 120. Alternatively, thecontrol signals CTRL and the data strobe signal DQS may be used toidentify the plurality of data signals DQ that are exchanged between thememory controller 110 and the nonvolatile memory device 120.

In response to the received signals, the nonvolatile memory device 120may receive the data “DATA” from the memory controller 110 or maytransfer the data “DATA” to the memory controller 110. For example, thenonvolatile memory device 120 may identify the command CMD, the addressADDR, or the data “DATA” of the plurality of data signals DQ by usingthe control signals CTRL.

In an exemplary embodiment of the inventive concept, the nonvolatilememory device 120 may include a NAND flash memory. However, theinventive concept is not limited thereto. For example, the nonvolatilememory device 120 may include at least one of volatile or nonvolatilememories such as a static random access memory (SRAM), a dynamic RAM(DRAM), a synchronous DRAM (SDRAM), a read only memory (ROM), aprogrammable ROM (PROM), an electrically programmable ROM (EPROM), anelectrically erasable and programmable ROM (EEPROM), a flash memory, aphase-change RAM (PRAM), a magnetic RAM (MRAM), a resistive RAM (RRAM),a ferroelectric RAM (FRAM), and the like.

FIG. 2 illustrates a memory controller illustrated in FIG. 1.

The memory controller 110 includes at least one processor 111, an errorcheck and correction engine 112, a host interface circuit 113, a RAMcontroller 114, and a nonvolatile memory interface circuit 115.

The processor 111 may control overall operations of the memorycontroller 110. The processor 111 may drive various firmware/software tocontrol the nonvolatile memory device 120. For example, the processor111 may drive a flash translation layer for managing a mapping table inwhich a relationship between logical addresses of a host device andphysical addresses of the nonvolatile memory device 120 is defined.

The ECC engine 112 may generate an error correction code for write datato be stored in the nonvolatile memory device 120. The ECC engine 112may detect and correct an error of read data based on an errorcorrection code read from the nonvolatile memory device 120.

The host interface circuit 113 may perform communication with the hostdevice by using a bus having various communication protocols. Forexample, a format of the bus may include one or more of variousinterface protocols such as universal serial bus (USB), small computersystem interface (SCSI), peripheral component interconnect express(PCIe), mobile PCIe (M-PCIe), advanced technology attachment (ATA),parallel ATA (PATA), serial ATA (SATA), serial attached small computersystem interface (SCSI) (SAS), integrated drive electronics (IDE),enhanced IDE (EIDE), nonvolatile memory express (NVMe), and universalflash storage (UFS).

The RAM controller 114 may provide interfacing between the memorycontroller 110 and a RAM. The RAM controller 114 may access the RAM inresponse to a request of the processor 111 or any other intellectualproperty (IP). For example, the RAM controller 114 may record data atthe RAM depending on a write request of the processor 111.Alternatively, the RAM controller 114 may read data from the RAMdepending on a read request of the processor 111.

The nonvolatile memory interface circuit 115 may perform communicationwith the nonvolatile memory device 120.

FIG. 3 illustrates a nonvolatile memory device of FIG. 1. Thenonvolatile memory device 120 may include a memory cell array 121, anaddress decoder 122, a page buffer 123, an input/output circuit 124, anda control logic circuit 125.

The memory cell array 121 may include the plurality of memory blocksBLK1 to BLKm. Each of the memory blocks BLK1 to BLKm may include aplurality of cell strings. Each of the cell strings includes a pluralityof memory cells. The plurality of memory cells may be connected to aplurality of word lines WL. Each of the memory cells may include asingle level cell (SLC) storing one bit or a multi-level cell (MLC)storing at least two bits.

The address decoder 122 is connected to the memory cell array 121through the plurality of word lines WL, string selection lines SSL, andground selection lines GSL. The address decoder 122 may receive alogical address and may decode the received logical address to drive theplurality of word lines WL. For example, the address ADDR may indicate aphysical address that is obtained by translating a logical address. Thistranslation operation may be performed by the flash translation layer(FTL) that is driven by the memory controller 110 (refer to FIG. 1), forexample.

The page buffer 123 is connected to the memory cell array 121 through aplurality of bit lines BL. Under control of the control logic circuit125, the page buffer 123 may control the bit lines BL such that the data“DATA” received from the input/output circuit 124 are stored in thememory cell array 121. Under control of the control logic circuit 125,the page buffer 123 may read data stored in the memory cell array 121and may transfer the read data to the input/output circuit 124. The pagebuffer 123 may receive data from the input/output circuit 124 in theunit of page or may read data from the memory cell array 121 in the unitof page.

The input/output circuit 124 may receive the data “DATA” from theoutside and may provide the received data “DATA” to the page buffer 123.

The control logic circuit 125 may receive the command CMD and thecontrol signals CTRL from the outside and may control the addressdecoder 122, the page buffer 123, and the input/output circuit 124 inresponse to the received command and control signals CMD and CTRL. Forexample, the control logic circuit 125 may control other components inresponse to the command and control signals CMD and CTRL such that thedata “DATA” are stored in the memory cell array 121. Alternatively, thecontrol logic circuit 125 may control other components in response tothe command and control signals CMD and CTRL such that the data “DATA”stored in the memory cell array 121 are transferred to the outside. Thecontrol signals CTRL may include signals that the memory controller 110provides to control the nonvolatile memory device 120.

The control logic circuit 125 may generate various voltages used by thenonvolatile memory device 120 to operate. For example, the control logiccircuit 125 may generate a plurality of program voltages, a plurality ofpass voltages, a plurality of selection read voltages, a plurality ofnon-selection read voltages, a plurality of erase voltages, a pluralityof verify voltages, etc. The control logic circuit 125 may provide thegenerated voltages to the address decoder 122 or to a substrate of thememory cell array 121.

FIG. 4 is a circuit diagram illustrating a memory block BLK of aplurality of memory blocks included in a memory cell array of FIG. 3.

The memory block BLK includes a plurality of cell strings CS11, CS12,CS21, and CS22. The plurality of cell strings CS11, CS12, CS21, and CS22may be arranged in a row direction and a column direction to form rowsand columns.

Each of the plurality of cell strings CS11, CS12, CS21, and CS22includes a plurality of cell transistors. For example, each of theplurality of cell strings CS11, CS12, CS21, and CS22 may include stringselection transistor SSTa and SSTb, a plurality of memory cells MC1 toMC128, ground selection transistors GSTa and GSTb, and dummy memorycells DMC and DMC2. The cell transistors may be stacked in a heightdirection that is a direction perpendicular to a plane defined by therow direction and the column direction. Each of the cell transistors maybe a charge trap flash (CTF) memory cell.

In each of the cell strings CS11, CS12, CS21, and CS22, the plurality ofmemory cells MC1 to MC128 are connected in series. The string selectiontransistors SSTa and SSTb are connected in series. Theserially-connected string selection transistors SSTa and SST areprovided between a bit line BL1 or BL2 and the serially-connected memorycells MC1 to MC128. The ground selection transistors GSTa and GSTb areconnected in series. The serially-connected ground selection transistorsGSTa and GSTb are provided between the serially-connected memory cellsMC1 to MC128 and a common source line CSL. The first dummy memory cellDMC1 is provided between the serially-connected memory cells MC1 toMC128 and the serially-connected ground selection transistors GSTa andGSTb. The second dummy memory cell DMC2 is provided between theserially-connected string selection transistors SSTa and SSTb and theserially-connected memory cells MC1 to MC128.

The ground selection transistors GSTa and GSTb may be connected incommon to a ground selection line GSL. Alternatively, ground selectiontransistors of the same row may be connected to the same groundselection line. For example, the first ground selection transistors GSTaof the cell strings CS11 and CS12 in the first row may be connected to afirst ground selection line, and the first ground selection transistorsGSTa of the cell strings CS21 and CS22 in the second row may beconnected to a second ground selection line. Alternatively, groundselection transistors that are provided at the same height from asubstrate may be connected to the same ground selection line. Forexample, the first ground selection transistors GSTa of the cell stringsCS11, CS12, CS21, and CS22 may be connected to the first groundselection line, and the second ground selection transistors GSTb of thecell strings CS11, CS12, CS21, and CS22 may be connected to the secondground selection line.

Memory cells of the same height from the substrate (or the groundselection transistors GSTa and GSTb) are connected in common to the sameword line. In addition, memory cells arranged at different heights fromthe substrate (or the ground selection transistors GSTa and GSTb) may beconnected to different word lines. For example, the memory cells MC1 toMC128 of the cell strings CS11, CS12, CS21, and CS22 are connected toword lines WL1 to WL128.

String selection transistors, which belong to the same row, from amongthe first string selection transistors SSTa of the same height areconnected to the same string selection line. For example, the firststring selection transistors SSTa of the cell strings CS11 and CS12 inthe first row are connected in common to a string selection line SSL1 a,and the first string selection transistors SSTa of the cell strings CS21and CS22 in the second row are connected in common to a string selectionline SSL2 a.

Likewise, string selection transistors, which belong to the same row,from among the second string selection transistors SSTb of the sameheight are connected to the same string selection line. For example, thesecond string selection transistors SSTb of the cell strings CS11 andCS12 in the first row are connected in common to a string selection lineSSL1 b, and the second string selection transistors SSTb of the cellstrings CS21 and CS22 in the second row are connected in common to astring selection line SSL2 b.

Dummy memory cells of the same height are connected to the same dummyword line. For example, the first dummy memory cells DMC1 are connectedto a first dummy word line DWL1, and the second dummy memory cells DMC2are connected to a second dummy word line DWL2.

In the memory block BLK, read and write operations may be performed inthe unit of a row. For example, a row of the memory block BLK may beselected by the string selection lines SSL1 a, SSL1 b, SSL2 a, and SSL2b.

When a turn-on voltage is supplied to the string selection lines SSL1 aand SSL1 b and a turn-off voltage is supplied to the string selectionlines SSL2 a and SSL2 b, the cell strings CS11 and CS12 in a first roware connected to the bit lines BL1 and BL2, respectively. When theturn-on voltage is supplied to the string selection lines SSL2 a andSSL2 b and the turn-off voltage is supplied to the string selectionlines SSL1 a and SSL1 b, the cell strings CS21 and CS22 in the secondrow are respectively connected to the bit lines BL1 and BL2. As a wordline is driven, memory cells (having the same height) connected to thedriven word line from among the memory cells MC1 to MC128 of the cellstrings CS11 to CS22 are selected. A read/write operation may beperformed on the selected memory cells. The selected memory cells mayconstitute a page unit.

For example, in the case where each of the memory cells MC1 to MC128 isa triple level cell (TLC) storing 3-bit data, memory cells connected toone word line may store three pages. Three pages that are stored inmemory cells connected to one word line may include a least significantbit (LSB) page, a center significant bit (CSB) page, and a mostsignificant bit (MSB) page. However, the inventive concept is notlimited thereto. For example, each memory cell may be implemented with aquad level cell (QLC) storing 4-bit data or any other type of memorycell storing five or more data bits. For example, each memory cell maybe implemented with a penta level cell (PLC) storing 5-bit data or ahexa level cell (HLC) storing 6-bit data.

Additionally, according to an exemplary embodiment of the presentinventive concept, pages of memory cells connected to a selected wordline include a fast read page and a normal read page. The fast read pagerefers to a page in which data are determined by one read voltage. Inother words, only one read voltage may be used to determine data of thefast read page. The normal read page refers to a page in which data aredetermined by a plurality of read voltages. In other words, more thanone read voltage is used to determine data of the normal read page. Inthe case that one of the pages of the memory cells connected to aselected word line is programmed to be the fast read page, both SLCprogramming and MLC programming (or QLC programming) may be performed onthe pages of the memory cells connected to the selected word line. Thiswill be described later.

In the memory block BLK, an erase operation may be performed for eachmemory block or for each sub-block. When an erase operation is performedfor each memory block, all the memory cells MC1 to MC128 of the memoryblock BLK may be simultaneously erased according to one erase request.When the erase operation is performed for each sub-block, some of thememory cells MC1 to MC128 of the memory block BLK may be simultaneouslyerased according to one erase request, and the remaining memory cells ofthe memory block BLK may be erase-inhibited. A low voltage (e.g., aground voltage) may be supplied to a word line connected to memory cellsto be erased, and a word line connected to erase-inhibited memory cellsmay be floated.

It is to be understood that the memory block BLK illustrated in FIG. 4is merely exemplary. The number of cell strings, the number of rows ofcell strings, and the number of columns of cell strings may be variable.In addition, in the memory block BLK, the number of string selectiontransistors, the number of dummy memory cells, the number of memorycells, and/or the number of ground selection transistors may increase ordecrease, and the height of the memory block BLK may increase ordecrease depending on the number of cell transistors. In addition, thenumber of string selection lines, the number of dummy word lines, thenumber of word lines, and/or the number of ground selection lines mayvary depending on the number of string selection transistors, the numberof dummy memory cells, the number of memory cells, and/or the number ofground selection transistors.

FIG. 5 illustrates an operating method of a storage device according toan exemplary embodiment of the present inventive concept. A method inwhich an SLC program operation and a TLC program operation are performedtogether on memory cells connected to a selected word line will bedescribed with reference to FIGS. 1, 3, and 5.

In operation S110, the nonvolatile memory device 120 receives a programcommand, an address, and page data associated with each page of aselected word line from the memory controller 110. For example, in thecase where the TLC program operation is performed on the nonvolatilememory device 120, a program command, an address, and page data may berepeatedly received three times. In the case where the QLC programoperation is performed on the nonvolatile memory device 120, a programcommand, an address, and page data may be repeatedly received fourtimes.

In operation S120, based on the program command, the address, and thepage data received from the memory controller 110, memory cellsconnected to the selected word line are programmed to have a fast readpage. The fast read page may be a page in which data are determined byone read voltage. To accomplish this, a special bit ordering may beused. For example, data including continuous bits of “1” and continuousbits of “0” may be stored in the fast read page. In other words, thedata may have one transition from bit “1” to bit “0” (or from bit “0” tobit “1”). More specifically, the data of the fast read page may havejust one bit transition.

Data of each normal read page may be composed of a combination of bit“1” and bit “0”. However, as the number of data bits to be stored ineach memory cell increases, the number of transitions from bit “1” tobit “0” (or from bit “0” to bit “1”) may increase. Hereinafter, atransition from bit “1” to bit “0” or from bit “0” to bit “1” may bereferred to as a “bit transition.” In an exemplary embodiment of theinventive concept, the number of bit transitions of data of each normalread page (or the number of periods in each of which bit “1” and bit “0”of data of each normal read page are switched) may be mostly identical.In particular, data of at least two of normal read pages other than afast read page may include the same number of bit transitions. Forexample, a first normal read page and a second normal read page may eachhave four bit transitions.

FIG. 6 is a timing diagram for describing an operating method of astorage device described with reference to FIG. 5.

Referring to FIGS. 1, 5, and 6, the nonvolatile memory device 120 mayreceive first page data PD1, second page data PD2, and third page dataPD3 from the memory controller 110.

During a first page setup part, the nonvolatile memory device 120 mayreceive a command CM1, a first address ADD1, the first page data PD1,and a command CM11 through a data line. The data line may be connectedbetween the nonvolatile memory device 120 and the memory controller 110.The commands CM1 and CM11 may be a command set for setting up the firstpage data PD1. The first address ADD may correspond to an area of memorycells, in which the first page data PD1 are to be programmed, from amongmemory cells connected to a selected word line. The nonvolatile memorydevice 120 may dump the first page data PD1 received through the dataline in response to the command CM11. A busy signal R/B may be in a busystate while the first page data PD1 are dumped. In FIG. 6, tR maycorrespond to a read access cycle time.

During a second page setup part, the nonvolatile memory device 120 mayreceive the command CM1, a second address ADD2, the second page dataPD2, and a command CM12. The commands CM1 and CM12 may be a command setfor setting up the second page data PD2. The second address ADD2 maycorrespond to an area of memory cells, in which the second page data PD2are to be programmed, from among the memory cells connected to theselected word line. The nonvolatile memory device 120 may dump thesecond page data PD2 received through the data line in response to thecommand CM12. The busy signal R/B may be in a busy state while thesecond page data PD2 are dumped.

During a third page setup part, the nonvolatile memory device 120 mayreceive the command CM1, a third address ADD3, the third page data PD3,and a command CM13. The commands CM1 and CM13 may be a command set forsetting up the third page data PD3. The third address ADD3 maycorrespond to an area of memory cells, in which the third page data PD3are to be programmed, from among the memory cells connected to theselected word line. The nonvolatile memory device 120 may dump the thirdpage data PD3 received through the data line in response to the commandCM13. The busy signal R/B may be in a busy state while the third pagedata PD3 are dumped.

Afterwards, in a program confirm part, the nonvolatile memory device 120may receive a command CM21, a fourth address ADD4, and a command CM22.The commands CM21 and CM22 may be a program confirm command set forinitiating a program operation. In an exemplary embodiment of theinventive concept, the fourth address ADD4 may include information abouta program order.

The nonvolatile memory device 120 may perform a program operation on thereceived page data PD1, PD2, and PD3 during a program time tPROG, inresponse to the command CM22. During the program time tPROG, the busysignal R/B may be in a busy state (e.g., in a low state).

As described above, the nonvolatile memory device 120 may continuouslyor sequentially receive a plurality of page data corresponding to oneselected word line and may perform a program operation after theplurality of page data are completely received. However, the inventiveconcept is not limited thereto. In the case where the number of databits to be stored per memory cell exceeds “3”, the number of page setupparts in which a command, an address, and page data are received mayincrease as much as the number of data bits has increased.

In an exemplary embodiment of the inventive concept, one of the first tothird page setup parts may correspond to a fast read page. For example,in the case where the second page setup part corresponds to a fast readpage, the second address ADD2 may indicate an address of an SLC pagewhere the second page data PD2 are programmed. However, a page setuppart corresponding to a fast read page is not limited to the second pagesetup part. For example, a fast read page may correspond to a differentpage setup part depending on a bit ordering for distinguishing betweenrespective program states.

FIG. 7 illustrates a bit ordering and threshold voltage distributions ofmemory cells programmed based on the bit ordering, according to anexemplary embodiment of the present inventive concept.

Below, a description will be given with reference to FIGS. 1, 3, and 7.The memory controller 110 may perform a TLC program, in which page dataare expressed by eight program states, with respect to memory cellsconnected to a selected word line. For example, the memory controller110 may program the memory cells connected to the selected word line inan incremental step pulse programming (ISPP) scheme, and may verify aprogram pass/fail by using a first verify voltage Vvfy1 to a seventhverify voltage Vvfy7.

In an exemplary embodiment of the inventive concept, the memorycontroller 110 programs the memory cells connected to the selected wordline such that data of one page of three pages are determined by oneread voltage. For example, the memory controller 110 programs the memorycells connected to the selected word line such that an erase state “E,”a first program state P1, a second program state P2 and a third programstate P3 of the center significant bit (CSB) page correspond to bit “1”.The memory controller 110 programs the memory cells connected to theselected word line such that a fourth program state P4, a fifth programstate P5, a sixth program state P6 and a seventh program state P7 of thecenter significant bit (CSB) page correspond to bit “0”. According tothis scheme, the CSB page includes one bit transition (e.g., a P3 to P4bit transition) where a bit value is changed. In other words, in thecase where the memory controller 110 performs a read operation on theCSB page, data of the CSB page may be determined by one read voltage. Inother words, the CSB page may have eight states including the erasestate “E”, but a data value of the CSB page may be determined by justone read voltage, thus obtaining an effect similar to the SLC program.

In an exemplary embodiment of the inventive concept, a bit ordering maybe based on a gray code. In other words, one bit value is changedbetween two adjacent program states. However, the bit ordering of thepresent inventive concept is not limited thereto. For example, two ormore bit values may be changed between two adjacent program states.However, in this case, the number of read voltages required to determineMSB page data and LSB page data may be greater than “3”.

In an exemplary embodiment of the inventive concept, data that arestored at a fast read page may be hot data that are targeted for afrequent read (or are frequently accessed by a memory controller).Alternatively, data that are stored at a fast read page may be data thatrequire high reliability. Alternatively, data that are stored at a fastread page may be data associated with the maintenance of a storagedevice, or meta data. Alternatively, data that are stored at a fast readpage may be data associated with an application to be quickly executedor launched according to a request of a user.

In contrast, data that are stored at a normal read page may be cold datathat are not targeted for a frequency read. Alternatively, data that arestored at a normal read page may be data that require relatively lowreliability. Alternatively, data that are stored at a normal read pagemay be data not associated with the maintenance of a storage device, oruser data.

Additionally, the memory controller 110 programs the remaining readpages of three pages other than a fast read page, based on a normal TLCprogram scheme. For example, as illustrated in FIG. 7, to determine dataof the MSB page, the MSB page may include three bit transitions (e.g.,between P1 and P2, between P4 and P5, and between P6 and P7), and theLSB page may include three bit transitions (e.g., between “E” and P1,between P2 and P3, and between P5 and P6). According to the abovedescription, with regard to pages corresponding to the selected wordline, the same number of read voltages used to determine data of theremaining pages (e.g., normal read pages) other than a fast read pagemay be identical.

FIG. 8 is a timing diagram for describing an operating method of astorage device according to an exemplary embodiment of the presentinventive concept.

Referring to FIGS. 1, 3, and 8, the nonvolatile memory device 120 mayreceive a command CM3, the address ADD2, and a command CM31 from thememory controller 110 through the data line. The commands CM3 and CM31may be a command set for reading data of a fast read page from thenonvolatile memory device 120. The address ADD2 may indicate an addresscorresponding to the fast read page.

In an exemplary embodiment of the inventive concept, the commands CM3and CM31 may be a normal read command. Alternatively, the commands CM3and CM31 may be a vendor-specific command for reading data from the fastread page. In response to the command CM31, the nonvolatile memorydevice 120 may transfer SLC page data R-DATA read from the fast readpage to the memory controller 110 through the data line.

FIG. 9 illustrates a fast read page read and a normal read page read ofa storage device when a read operation is performed according to anexemplary embodiment of FIG. 8. For better understanding, a bit orderingof the present inventive concept, threshold voltage distributionsaccording to the bit ordering, and read voltages used for a madoperation of each page are illustrated together.

Referring to FIGS. 1 and 9, the MSB page has the following bit ordering:a bit value of each of the erase state “E” and the first program stateP1 is “1”, a bit value of each of the second to fourth program statesP2, P3, and P4 is “0”, a bit value of each of the fifth and sixthprogram states P5 and P6 is “1”, and a bit value of the seventh programstate P7 is “0”. The MSB page has three bit transitions. The CSB pagehas the following bit ordering: a bit value of each of the erase state“E” and the first to third program states P1, P2, and P3 is “1”, a bitvalue of each of the fourth to seventh program states P4, P5, P6, and P7is “0”. The CSB page has one bit transition. The LSB page has thefollowing bit ordering: a bit value of the erase state “E” is “1”, a bitvalue of each of the first and second program states P1 and P2 is “0”, abit value of each of the third to fifth program states P3, P4, and P5 is“1”, and a bit value of each of the sixth and seventh program states P6and P7 is “0”. The LSB page has three bit transitions.

In an exemplary embodiment of the inventive concept, maximally threeread voltages VRD2, VRD5, and VRD7 may be required to read data of theMSB page. For example, the fifth read voltage VRD5, the second readvoltage VRD2, and the seventh read voltage VRD7 may be sequentiallyapplied to a memory cell as a read voltage, but the present inventiveconcept is not limited thereto. For example, firstly, the fifth readvoltage VRD5 may be applied to a memory cell having the first programstate P1 for the purpose of determining MSB page data of the memorycell. In this case, it may be determined that the memory cell is anon-cell, but whether it has a value of “1” or a value of “0” may befurther determined. Afterwards, the second read voltage VRD2 may beapplied to the memory cell. In this case, it may be determined that thememory cell is an on-cell, and thus, the memory cell may be finallydetermined to have a value of “1”.

In an exemplary embodiment of the inventive concept, only one readvoltage VRD4 may be required to read data of the CSB page. For example,in the case where a memory cell has one of the erase state “E” to thethird program state P3, the memory controller 110 may apply the fourthread voltage VRD4 to the memory cell to read data stored in the memorycell, and the memory cells may be determined as an on-cell. In the CSBpage, because memory cells having threshold voltages smaller than thefourth read voltage VRD4 store a bit value of “1”, an additional readvoltage for determination is not required.

In the case where a memory cell has one of the fourth program state P4to the seventh program state P7, the memory controller 110 may apply thefourth read voltage VRD4 to the memory cell to read data stored in thememory cell, and the memory cells may be determined as an off-cell. Inthe CSB page, because memory cells having threshold voltages greaterthan the fourth read voltage VRD4 store a bit value of “0” an additionalread voltage for determination is not required.

In an exemplary embodiment of the inventive concept, maximally threeread voltages VRD1, VRD3, and VRD6 may be required to read data of theLSB page. For example, the third read voltage VRD3, the first readvoltage VRD1, and the sixth read voltage VRD6 may be sequentiallyapplied to a memory cell as a read voltage, but the present inventiveconcept is not limited thereto. For example, firstly, the third readvoltage VRD3 may be applied to a memory cell having the fourth programstate P4 to determine LSB page data of the memory cell. In this case, itmay be determined that the memory cell is an off-cell, but whether ithas a value of “1” or a value of “0” may be further determined.Afterwards, the sixth read voltage VRD6 may be applied to the memorycell. In this case, it may be determined that the memory cell is anon-cell, and thus, the memory cell may be finally determined to have avalue of “1”.

According to the above description, because only one read voltage (e.g.,VRD4) is required to determine data of a fast read page, a read speed ofa particular page is increased. Because data of normal read pages aredetermined by using the same number of read voltages, a uniform readspeed may be secured with regard to the normal read pages.

Although FIG. 9 illustrates the CSB page as a fast read page, theinventive concept is not limited thereto. For example, a bit orderingthat is different from the bit ordering illustrated in FIG. 9 may beused. In this case, a fast read page may be an MSB page or an LSB page.

FIG. 10 illustrates a page read of a storage device when a readoperation of the storage device is performed according to a normal bitordering.

First, like the bit ordering of the inventive concept described above, abit ordering illustrated in FIG. 10 is based on a gray code. However,according to the bit ordering of FIG. 10, the number of read voltagesused to perform a read operation on each page is mostly identical, andthus, read speeds of the pages are uniform. For example, two readvoltages VRD1 and VRD5 are required to determine data of the MSB page,three read voltages VRD2, VRD4, and VRD6 are required to determine dataof the CSB page, and two read voltages VRD3 and VRD7 are required todetermine data of the LSB page.

According to the bit ordering illustrated in FIG. 10, because the numberof read voltages required to determine data of the CSB page is mostlyidentical to the number of read voltages required to determine data ofeach of the MSB and LSB pages, read speeds of the respective pages maybe relatively uniform. In contrast, according to the bit ordering of thepresent inventive concept illustrated in FIG. 9, a read speed that issubstantially identical to a read speed of an SLC page may be secured byusing the fast read page.

FIG. 11 illustrates a bit ordering according to an exemplary embodimentof the present inventive concept.

The embodiment of FIG. 11 illustrates a bit ordering associated with aQLC that stores 4-bit data. For example, the bit ordering of FIG. 11 isbased on a gray code. The memory controller 110 (refer to FIG. 1) mayperform a QLC program, in which page data are expressed by 15 programstates, with respect to memory cells connected to a selected word line.The program process is similar to that described with reference to FIGS.5 and 6, and thus, additional description may be omitted to avoidredundancy.

According to the bit ordering of the MSB page illustrated in FIG. 11,the MSB page may include four bit transitions (e.g., between P2 and P3,between P6 and P7, between P8 and P9, and between P12 and P13). In otherwords, the number of read voltages required to determine data of the MSBpage is 4 (VRD3, VRD7, VRD9, and VRD13). The number of read voltagesrequired to determine data of a 3^(rd) significant bit (3SB) page is 5(VRD2, VRD4, VRD6, VRD11, and VRD15) since the number of bit transitionsis 5, and the number of read voltages required to determine data of a2^(nd) significant bit (2SB) page is 5 (VRD1, VRD5, VRD10, VRD12, andVRD14) since the number of bit transitions is 5. The three pagesdescribed above, in other words, the MSB page, the 3SB page, and 2SBpage may be referred to as “normal read pages”. In an exemplaryembodiment of the inventive concept, normal pages may not include atleast two pages in which the number of read voltages required todetermine data increases in order of a power of two.

In the LSB page, a bit value of each of the erase state “E” to theseventh program state P7 is “1”, and a bit value of each of the eighthprogram state P8 to fifteenth program state P15 is “0”. According tothis bit ordering, the number of read voltages required to determinedata of the LSB page is 1 (VRD8). This is so, because there is only onebit transition. For example, in the case where a memory cell has one ofthe eighth program state P8 to the fifteenth program state P15, thememory controller 110 may apply only the eighth read voltage VRD8 to thememory cell to read data stored in the memory cell. As a result, thememory cells may be determined as an off-cell. In the LSB page, becausememory cells having threshold voltages greater than the eighth readvoltage VRD8 store a bit value of “0”, an additional read voltage fordetermination is not required.

According to the above description, because only one read voltage (e.g.,VRD8) is required to determine data of a fast read page, a read speed ofthe fast read page (e.g., the LSB page) is increased. Through this bitordering, it is possible to obtain substantially the same effect as thatobtained in the case of reading data from SLC-programmed memory cells.In addition, the number of read voltages necessary to determine data ofeach of normal read pages (e.g., the MSB page, the 3SB page, and the 2SBpage) other than the fast read page is mostly identical. For example,with regard to at least two of the normal read pages, the number of readvoltages necessary to determine data is identical. In FIG. 11, the 3SBpage and the 2SB page use the same number of read voltages.

FIG. 12 illustrates a bit ordering according to an exemplary embodimentof the present inventive concept.

The embodiment of FIG. 11 illustrates a bit ordering associated with apenta level cell (PLC) that stores 5-bit data. For example, the bitordering of FIG. 12 is based on a gray code. The memory controller 110(refer to FIG. 1) may perform a PLC program, in which page data areexpressed by 31 program states, with respect to memory cells connectedto a selected word line. The program process is similar to thatdescribed with reference to FIGS. 5 and 6, and thus, additionaldescription may be omitted to avoid redundancy.

According to the bit ordering of the LSB page illustrated in FIG. 12,the LSB page may include eight bit transitions (e.g., between “E” andP1, between P4 and P5, between P9 and P10, between P11 and P12, betweenP13 and P14, between P16 and P17, between P22 and P23, and between P29and P30). In other words, the number of read voltages required todetermine data of the LSB page is 8 (VRD1, VRD5, VRD10, VRD12, VRD14,VRD17, VRD23, and VRD30).

The number of read voltages required to determine data of a 2SB page is8 (VRD2, VRD9, VRD15, VRD18, VRD20, VRD24, VRD27, and VRD29), the numberof read voltages required to determine data of a 3SB page is 7 (VRD3,VRD6, VRD8, VRD13, VRD21, VRD25, and VRD28), and the number of readvoltages required to determine data of a 4th significant bit (4SB) pageis 7 (VRD4, VRD7, VRD11, VRD19, VRD22, VRD26, and VRD31). The four pagesdescribed above, in other words, the LSB page, the 2SB page, the 3SBpage, and the 4SB page may be referred to as “normal read pages”.

In the MSB page, a bit value of each of the erase state “E” to thefifteenth program state P15 is “1”, and a bit value of each of thesixteenth program state P16 to the 31st program state P31 is “0”.According to this bit ordering, the number of read voltages required todetermine data of the MSB page is 1 (VRD16). For example, in the casewhere a memory cell has one of the sixteenth program state P16 to the31st program state P31, the memory controller 110 may apply only thesixteenth read voltage VRD16 to the memory cell to read data stored inthe memory cell. As a result, the memory cells may be determined as anoff-cell. In the MSB page, because memory cells having thresholdvoltages greater than the sixteenth read voltage VRD16 store a bit valueof “0”, an additional read voltage for determination is not required.

As a result, by using the bit ordering illustrated in FIG. 12, a readspeed of a fast read page (e.g., the MSB page) is increased. Throughthis bit ordering, it is possible to obtain substantially the sameeffect as that obtained in the case of reading data from SLC-programmedmemory cells. For example, according to the bit ordering illustrated inFIG. 12, with regard to at least two normal read pages, the number ofread voltages necessary to determine data is identical. For example, thenumber of read voltages necessary to determine data is 8 in the case ofthe LSB page and the 2SB page; and the number of read voltages necessaryto determine data is 7 in the case of the 3SB page and the 4SB page.

FIG. 13 illustrates a bit ordering according to an exemplary embodimentof the present inventive concept.

Like the embodiment of FIG. 12, the embodiment of FIG. 13 illustrates abit ordering of a PLC that stores 5-bit data. For example, the bitordering of FIG. 13 is based on a gray code.

According to the bit ordering of the LSB page illustrated in FIG. 13,the LSB page may include 15 bit transitions (e.g., between “E” and P1,between P2 and P3, between P3 and P4, between P6 and P7, between P8 andP9, between P10 and P1, between P12 and P13, between P14 and P15,between P16 and P17, between P18 and P19, between P20 and P21, betweenP22 and P23, between P25 and P26, between P28 and P29, and between P30and P31). In other words, the number of read voltages required todetermine data of the LSB page is 15 (VRD1, VRD3, VRD5, VRD7, VRD9,VRD11, VRD13, VRD15, VRD17, VRD19, VRD21, VRD23, VRD26, VRD29, andVRD31).

The number of read voltages required to determine data of a 2SB page is9 (VRD2, VRD6, VRD10, VRD14, VRD18, VRD22, VRD25, VRD27, and VRD30), thenumber of read voltages required to determine data of a 3SB page is 4(VRD4, VRD12, VRD20, and VRD28), and the number of read voltagesrequired to determine data of a 4SB page is 2 (VRD8 and VRD24). The fourpages described above, in other words, the LSB page, the 2SB page, the3SB page, and the 4SB page may be referred to as “normal read pages”.

In the MSB page, a bit value of each of the erase state “F” to thefifteenth program state P15 is “1”, and a bit value of each of thesixteenth program state P16 to the 31st program state P31 is “0”.According to this bit ordering, the number of read voltages required todetermine data of the MSB page is 1 (VRD16). Regardless of whether amemory cell has any program state, only the sixteenth read voltage VRD16is required to determine data stored in the memory cell, and anadditional read voltage for determination is not required.

According to this bit ordering, a hierarchical memory may be implementedby allowing pages of memory cells connected to a selected word line tohave different read speeds. For example, data that requires the highestreliability or requires the fastest read speed may be stored at the MSBpage. In contrast, data that does not require the highest reliability ordoes not require the fastest read speed may be stored at the LSB page.Depending on required reliability and/or a required read speed, data maybe stored at an appropriate page of the 2SB page, the 3SB page, and the4SB page.

According to the exemplary embodiments of the inventive conceptdescribed above, a memory area may be prevented from being wasted byperforming only the SLC program on memory cells connected to a selectedword line. For example, assuming the case where an entire memory blockis SLC-programmed and provides a capacity of 1 MB. In this case, whenthe entire memory block is TLC-programmed, the memory block provides acapacity of 3 MB. In addition, when the entire memory block isQLC-programmed, the memory block provides a capacity of 4 MB. In otherwords, when the entire memory block is SLC-programmed, the loss of amemory space is considerable.

However, according to an exemplary embodiment of the inventive concept,memory cells connected to a selected word line include a fast read pagein which data are determined by using one read voltage, as well asnormal read pages in which data are determined by using a plurality ofread voltages. Because data of the fast read page are determined byusing only one read voltage, it is possible to obtain substantially thesame effect as that obtained by the SLC program. In other words, a readspeed of the fast read page is identical to a read speed of an SLC pagein which one bit is stored per memory cell. In addition, a storage areamay be prevented from being wasted by using the SLC program.

FIG. 14 illustrates a portion of a circuit diagram of FIG. 4. A physicallocation of a memory block, at which a fast read page according to anexemplary embodiment of the present inventive concept is stored, will bedescribed with reference to FIGS. 12 to 14 together.

The MLC, TLC, QLC, and PLC, each of which stores a plurality of bits,are prone to deterioration compared with the SLC that stores one bit.For example, as the number of bits to be stored per cell increases, thedeterioration may worsen. Accordingly, the SLC program may be performedon memory cells connected to a word line (e.g., WL1, or WL1 and WL2)adjacent to the ground selection transistors GSTa and GSTb. As adistance from the ground selection transistors GSTa and GSTb increases,the number of data bits to be stored in a memory cell may increase.

In an exemplary embodiment of the inventive concept, the SLC program maybe performed on memory cells MC1 and MC2 connected to the first wordline WL1 and the second word line WL2. The PLC program may be performedon memory cells MC3 connected to the third word line WL3. In this case,according to the bit ordering illustrated in FIG. 12, the MSB page maybe a fast read page that requires one read voltage to determine data,and the remaining pages may be normal read pages.

The SLC program may be performed on memory cells connected to a wordline (e.g., WL127, or WL127 and WL128) adjacent to the string selectiontransistors SSTa and SSTb. As a distance from the string selectiontransistors SSTa and SSTb increases, the number of data bits to bestored in a memory cell may increase. The PLC program may be performedon memory cells connected to the 126th word line WL126. The MSB page ofpages of memory cells connected to the 126th word line WL126 may be afast read page that requires one read voltage to determine data, and theremaining pages of the memory cells connected to the 126th word line maybe normal read pages.

In another exemplary embodiment of the inventive concept, the SLCprogram may be performed on memory cells MC1 connected to the first wordline WL1. The TLC program may be performed on memory cells MC2 connectedto the second word line WL2. In this case, the CSB page of pages ofmemory cells MC2 connected to the second word line WL2 may be a fastread page as described with reference to FIG. 9, and the LSB page andthe MSB page may be normal read pages. The QLC program may be performedon memory cells MC3 connected to the third word line WL3. In this case,the LSB page of pages of memory cells MC3 connected to the third wordline WL3 may be a fast read page that requires one read voltage todetermine data, and the remaining pages of the memory cells connected tothe third word line WL3 may be normal read pages.

Additionally, a scheme to program a fast read page depending on alocation of a word line is not limited to the above describedembodiments. In other words, a similar program method may be implementedsuch that the number of bits to be stored per memory cell increases as adistance from a ground selection transistor or a string selectiontransistor increases.

FIG. 15 illustrates an operating method of a storage device according toan exemplary embodiment of the present inventive concept. A method inwhich a fast read page is performed on memory cells connected to aselected word line will be described with reference to FIGS. 1, 3, and15.

In operation S210, the nonvolatile memory device 120 receives a firstprogram command, a first address, and first data from the memorycontroller 110. The first program command may be associated with the SLCprogram, and the first address may be associated with an address of apage where the SLC program is performed.

In an exemplary embodiment of the inventive concept, the first data maybe hot data targeted for a frequent read. Alternatively, the first datamay be data that require high reliability. Alternatively, the first datamay be data associated with the maintenance of a system device, or metadata. Alternatively, the first data may be data associated with anapplication to be quickly executed depending on a request of the user.

In operation S220, the first data may be programmed in memory cellsconnected to a first selected word line through the SLC program.

In operation S230, the nonvolatile memory device 120 receives a secondprogram command, a second address, and second data from the memorycontroller 110. The second program command may be associated with theTLC program, the QLC program, or the PLC program, and the second addressmay be associated with an address of a page where the TLC/QLC/PLCprogram is performed.

In an exemplary embodiment of the inventive concept, unlike the firstdata, the second data may be data that do not require high reliability.Alternatively, the second data may be data that are not associated withthe maintenance of a system device or are not meta data. In operationS240, memory cells connected to a second selected word line areprogrammed based on first data previously stored in the nonvolatilememory device 120, and the second command, the second address, and thesecond data received from the memory controller 110.

For example, the first data previously stored in the nonvolatile memorydevice 120 may be stored at the fast read page of the memory cellsconnected to the second selected word line. The second data receivedfrom the memory controller 110 may be stored at normal read pages of thememory cells connected to the second selected word line. For example, abit ordering forming the fast read page and the normal read pages may bebased on the bit ordering described with reference to FIG. 9, 11, 12, or13. Accordingly, data of the fast read page may be composed ofcontinuous bits of “1” and continuous bits of “0” such that a data valueof the fast read page is determined by one read voltage. However, thebit ordering is not limited to the bit orderings illustrated in FIGS. 9,11, 12, and 13. For example, the inventive concept may be applied tovarious bit orderings that make it possible to implement a fast readpage.

FIG. 16 is a timing diagram for describing an operating method of astorage device described with reference to FIG. 15. A program method forthe nonvolatile memory device 120 using a copy-back program with arandom data command will be described with reference to FIGS. 1, 15, and16 together. For example, FIG. 16 is associated with a program for theTLC that stores 3-bit data.

During a copy-back read, the nonvolatile memory device 120 may receive acommand CM4, an address ADD0, and a command CM41 from the memorycontroller 110. The commands CM4 and CM41 may be a command set forperforming the copy-back read on SLC page data stored at the addressADD0 of the nonvolatile memory device 120. The address ADD0 may be asource address at which SLC page data targeted for the copy-back arestored. In other words, the address ADD0 may be an SLC page address.

In response to the command CM41, the nonvolatile memory device 120 maytransfer SLC page data R-DATA stored at an area corresponding to theaddress ADD0 to the memory controller 110. For example, the SLC pagedata R-DATA may be hot data targeted for a frequent read, data requiringhigh reliability, data associated with the maintenance of a system, metadata, etc.

During a first page setup part, the nonvolatile memory device 120 mayreceive a command CM5, a first address ADD1, and first page data PD1from the memory controller 110. The command CM5 may be a command foragain programming the SLC page data R-DATA read from the nonvolatilememory device 120 in the nonvolatile memory device 120. In other words,the first page data PD1 may be identical to the SLC page data R-DATA.The first address ADD1 that is a portion of a destination address maycorrespond to a fast read page of pages of memory cells connected to aselected word line. The first address ADD1 may be different from theaddress ADD0 and may belong to a block that is identical to or differentfrom a memory block to which the address ADD0 belongs. The nonvolatilememory device 120 may dump the first page data PD1 in response to thecommand CM5.

During a second page setup part, the nonvolatile memory device 120 mayreceive the command CM5, a second address ADD2, second page data PD2,and a command CM51 from the memory controller 110. The command CM5 andCM51 may be commands for setting up the second page data PD2. The secondaddress ADD2 that is a portion of the destination address may correspondto a normal read page of the pages of the memory cells connected to theselected word line. The nonvolatile memory device 120 may dump thesecond page data PD2 in response to the command CM51.

During a third page setup part, the nonvolatile memory device 120 mayreceive the command CM5, a third address ADD3, third page data PD3, anda command CM52 from the memory controller 110. The command CM5 and CM52may be commands for setting up the third page data PD3. The thirdaddress ADD3 that is a portion of the destination address may correspondto a normal read page of the pages of the memory cells connected to theselected word line. The nonvolatile memory device 120 may dump the thirdpage data PD3 in response to the command CM52.

Three page setup parts for the TLC program have just been described asan example, but the number of page setup parts may vary depending on thenumber of data bits to be stored in a memory cell.

Afterwards, the first page data PD1, the second page data PD2, and thethird page data PD3 may be programmed in the memory cells connected tothe selected word line. In an exemplary embodiment of the inventiveconcept, a first page may be a fast read page in which data aredetermined by one read voltage, and a second page and a third page maybe normal read pages in which a plurality of read voltages are requiredto determine data.

FIG. 17 is a timing diagram for describing an operating method of astorage device described with reference to FIG. 15. The embodiment ofFIG. 17 is similar to the embodiment of FIG. 16 except that avendor-specific command is used instead of the copy-back command.Accordingly, a difference will be mainly described with reference toFIGS. 1, 15, and 17 together.

During an SLC data read, the nonvolatile memory device 120 may receive acommand CM6, an address ADD0, and a command CM61 from the memorycontroller 110. The nonvolatile memory device 120 may read SLC page dataR-DATA in response to the command CM61.

During a first page setup part, the nonvolatile memory device 120 mayreceive a command CM7, a first address ADD1, first page data PD1, and acommand CM71 from the memory controller 110. The nonvolatile memorydevice 120 may dump the SLC page data R-DATA in response to the commandCM71. Operations of a second page setup part and a third page setup partare similar to the above operation of the first page setup part. Forexample, during the second page setup part, the nonvolatile memorydevice 120 may receive the command CM7, a second address ADD2, secondpage data PD2, and a command CM72 from the memory controller 110, andduring the third page setup part, the nonvolatile memory device 120 mayreceive the command CM7, a third address ADD3, third page data PD3, anda command CM73 from the memory controller 110.

The above commands CM6 and CM7 may be vendor-specific commands forprogramming SLC page data previously stored in the nonvolatile memorydevice 120 and the first to third page data PD1 to PD3 newly received,in memory cells connected to a selected word line.

FIG. 18 is a table illustrating the average number of read voltagesrequired to determine page data depending on a page type.

As described above, in the fast read page according to an exemplaryembodiment of the inventive concept and a normal SLC page, the number ofread voltages necessary to determine page data is identically “1”.

The number of read voltages necessary to determine data of a normal readdata according to the bit ordering of an exemplary embodiment of theinventive concept is “3” in the case of the TLC. For example, the numberof read voltages necessary to determine data of each of the MSB and LSBpages according to the bit ordering illustrated in FIG. 9 is “3”, andthus, the average number of read voltages in each page may be “3”.

The number of read voltages necessary to determine data of a normal readpage according to the bit ordering of an exemplary embodiment of theinventive concept is “4.7” in the case of the QLC. For example,according to the bit ordering illustrated in FIG. 11, the number of readvoltages necessary to determine data of each of the 2SB, 3SB and MSBpages are “5”, “5” and “4”, respectively, and thus, the average numberof read voltages in each page may be “4.7”.

The number of read voltages necessary to determine data of a normal readpage according to the bit ordering of an exemplary embodiment of theinventive concept is “7.5” in the case of the PLC. For example,according to the bit ordering illustrated in FIG. 12, the number of readvoltages necessary to determine data of each of the 2SB, 3SB and MSBpages are “8”, “8” and “7”, respectively, and thus, the average numberof read voltages in each page may be “7.5”.

Unlike the bit orderings illustrated in FIGS. 9, 11, and 12, in the caseof a hexa level cell (HLC), the average number of read voltagesnecessary to determine data of a normal read page according to the bitordering of the inventive concept is “12.4”.

In FIG. 18, a page according to an existing bit ordering is expressed asa legacy page, and the average number of read voltages necessary todetermine data of the TLC page, the average number of read voltagesnecessary to determine data of the QLC page, the average number of readvoltages necessary to determine data of the PLC page, and the averagenumber of read voltages necessary to determine data of the HLC page are“2.3”, “3,8”, “6.2”, and “10.5”, respectively.

Comparing the number of read voltages necessary to determine data ofeach page according to the bit ordering of an exemplary embodiment ofthe inventive concept with the number of read voltages necessary todetermine data of each page according to an existing bit ordering, thenumber of read voltages for a normal read page an exemplary embodimentof the inventive concept may be a little bit more than the number ofread voltages for an existing legacy read page. The reason is thatmemory cells connected to a selected word line include a fast read pagein which data are determined by one read voltage. However, an exemplaryembodiment of the inventive concept is advantageous in consideration ofthe following: simultaneously programming a fast read page and normalread page at memory cells connected to a selected word line, securingthe reliability of data through the fast read page, and securing anadditional storage space compared to the case where the SLC program issolely performed.

FIG. 19A is a table illustrating a read time taken to determine pagedata depending on a page type, and FIG. 19B is a graph illustrating readtimes for respective page types of FIG. 19A.

Referring to FIGS. 19A and 19B, a read latency of a fast read pageaccording to the bit ordering of an exemplary embodiment of the presentinventive concept and a read latency of an SLC page according to anexisting bit ordering is identically 26 microseconds. As the number ofbits to be stored per memory cell increases, a read latency alsoincreases. For example, the normal read latency goes from 78 to 322microseconds and the legacy read latency goes from 61 to 273microseconds. Like the pattern obtained by analyzing the table of FIG.18, because the number of read voltages for a normal read page accordingto the bit ordering of an exemplary embodiment of the present inventiveconcept is somewhat more than the number of read voltages for a legacypage, a read latency of the normal read page is somewhat greater than aread latency of a legacy page. However, an exemplary embodiment of theinventive concept is advantageous in consideration of the following:securing the reliability of data through a fast read page and securingan additional storage space compared to the case where the SLC programis solely performed.

FIG. 20 is a graph illustrating the number of error bits associated withthe number of bits to be stored per memory cell, for each page type.

As understood from the graph, the number of error bits associated with afast read page according to the bit ordering of an exemplary embodimentof the present inventive concept is substantially identical to thenumber of error bits associated with an SLC page according to anexisting bit ordering.

However, in the case of a read operation for a normal read pageaccording to the bit ordering of an exemplary embodiment of the presentinventive concept, because the number of read voltages necessary todetermine page data is a few more than a legacy page, the number oferror bits of the normal read page is a few more than the number oferror bits of the legacy page. However, considering that the highreliability of data is secured through the fast read page, the increasein the number of error bits in the normal read page may be sufficientlyoffset.

FIG. 21 illustrates a storage system to which a memory controller and anonvolatile memory device according to an exemplary embodiment of theinventive concept are applied. A storage system 1000 may include a host1100 and a storage device 1200.

The storage device 1200 exchanges a signal SIG with the host 1100through a signal connector 1201 and is supplied with a power PWR througha power connector 1202. The storage device 1200 includes a solid statedrive (SSD) controller 1210, a plurality of nonvolatile memories 1221 to122 n, an auxiliary power supply 1230, and a buffer memory 1240. Each ofthe plurality of nonvolatile memories 1221 to 122 n may include anonvolatile memory device described with reference to FIGS. 1 to 20. Inother words, the nonvolatile memories 1221 to 122 n may include the fastread page according to the bit ordering described with reference toFIGS. 1 to 20

The SSD controller 1210 may control the nonvolatile memories 1221 to 122n in response to the signal SIG received from the host 1100. Thenonvolatile memories 1221 to 122 n may operate under control of the SSDcontroller 1210. The auxiliary power supply 1230 is connected with thehost 1100 through the power connector 1202. The auxiliary power supply1230 may be charged by the power PWR supplied from the host 1100. Whenthe power PWR is not smoothly supplied from the host 1100, the auxiliarypower supply 1230 may power the storage device 1200. The SSD controller1210 may be the memory controller 110 described with reference to FIGS.1 to 20.

FIG. 22 illustrates a memory card to which a nonvolatile memory deviceaccording to an exemplary embodiment of the inventive concept isapplied. Referring to FIG. 22, a memory card 2200 connected to a host2100 includes a memory controller 2210 and a nonvolatile memory device2220. The memory controller 2210 may include an SRAM 2212, a CPU 2213, ahost interface 2215, an ECC engine 2217, and a memory interface 2219.The memory controller 2210 is configured to perform a read operation anda write operation on the nonvolatile memory device 2220 depending on thebit ordering described with reference to FIGS. 1 to 20. The nonvolatilememory device 2220 may be implemented with various nonvolatile memorydevices such as a NAND flash memory device or a NOR flash memory device.For example, the memory controller 2210 and the nonvolatile memorydevice 2220 may be integrated in one semiconductor device to constitutea device such as a universal flash storage (UFS) card.

According to exemplary embodiments of the present inventive concept, aparticular page of pages of memory cells connected to a selected wordline is provided as a fast read page in which data are determined by oneread voltage.

According to exemplary embodiments of the present inventive concept,among the pages of the memory cells connected to the selected word line,the remaining pages other than the fast read page are provided as normalread pages.

As a result, it is possible to secure a fast read speed and thereliability of data through the fast read page and to secure a largedata capacity through the normal read pages.

While the inventive concept has been particularly shown and describedwith reference to exemplary embodiments thereof, it will be apparent tothose of ordinary skill in the art that various changes andmodifications may be made thereto without departing from the spirit andscope of the inventive concept as set forth in the following claims.

1. A nonvolatile memory device, comprising: a memory cell array, thememory cell array including a plurality of cell strings, at least one ofthe cell strings including a plurality of memory cells stacked in adirection perpendicular to a surface of a substrate, at least one of thememory cells is a multi-level cell storing at least three bits; and acontrol logic circuit configured to control a page buffer to read a fastread page of the memory cells with one read voltage and at least twonormal read pages of the memory cells with the same number of readvoltages.
 2. The nonvolatile memory device of claim 1, wherein only theone read voltage is used to read data of the fast read page.
 3. Thenonvolatile memory device of claim 2, wherein the data of the fast readpage is frequently accessed.
 4. The nonvolatile memory device of claim3, wherein a read or program operation is performed when the data of thefast read page is accessed.
 5. The nonvolatile memory device of claim 1,wherein at least three read voltages are used to read data of each ofthe at least two normal read pages.
 6. The nonvolatile memory device ofclaim 1, wherein a bit ordering of the fast read page has only one bittransition.
 7. The nonvolatile memory device of claim 1, wherein a bitordering of each of the at least two normal read pages has more than onebit transition.
 8. The nonvolatile memory device of claim 1, wherein theplurality of memory cells of the at least one cell string are disposedbetween a string select line and a ground select line.
 9. Thenonvolatile memory device of claim 8, wherein the at least one cellstring includes a dummy memory cell disposed between one of the memorycells and a string selection transistor or between one of the memorycells and a ground select transistor.
 10. The nonvolatile memory deviceof claim 1, wherein each of the memory cells is a charge trap flashtransistor.
 11. The nonvolatile memory device of claim 1, wherein themulti-level cell is a quad level cell, a penta level cell or a hexalevel cell.
 12. The nonvolatile memory device of claim 1, wherein thefast read page is one of a least significant bit page, a centersignificant bit page and a most significant bit page.
 13. Thenonvolatile memory device of claim 1, wherein the fast read page is aleast significant bit page, a most significant bit page or one of aplurality of center significant bit pages.
 14. The nonvolatile memorydevice of claim 1, wherein a first memory cell is programmed with singlelevel cell (SLC) data and a second memory cell is programmed with triplelevel cell (TLC), quad level cell (QLC), or penta level cell (PLC) data.15. The nonvolatile memory device of claim 14, wherein one of the TLC,QLC or PLC includes the fast read page and the normal read pages. 16-27.(canceled)
 28. A storage system, comprising: a storage device thatexchanges a signal with an external device, wherein the storage deviceincludes a memory controller and a plurality of nonvolatile memories,wherein at least one of the memories includes: a memory cell array, thememory cell array including a plurality of memory cells stacked in adirection perpendicular to a surface of a substrate; and a control logiccircuit configured to control a page buffer to read a fast read page ofthe memory cells with one read voltage and at least two normal readpages of the memory cells with the same number of read voltages.
 29. Thestorage system of claim 28, wherein the fast read page stores datatargeted for frequent reads.
 30. The storage system of claim 28, whereina bit ordering of the fast read page has only one bit transition, and abit ordering of each of the at least two normal read pages has more thanone bit transition.
 31. The storage system of claim 28, wherein thememory cells include multi-level cells storing at least three bits. 32.The system of claim 28, further comprising a power supply configured tosupply power to the memory controller.
 33. A memory device, comprising:a memory controller; and a nonvolatile memory device connected to thememory controller, wherein the memory controller is configured toperform a read operation on the nonvolatile memory device such that afast read page of the nonvolatile memory device is read with one readvoltage and at least two normal read pages of the nonvolatile memorydevice are read with the same number of read voltages.
 34. The memorydevice of claim 33, further comprising an interface for connecting to anexternal device.
 35. The memory device of claim 33, wherein a readlatency of the fast read page is shorter than a read latency of each ofthe normal read pages.
 36. The memory device of claim 33, wherein dataof the fast read page is more frequently accessed than data of each ofthe normal read pages.
 37. The memory device of claim 33, wherein thememory controller includes a memory interface for data communicationwith the nonvolatile memory device.